ASML and TSMC achieve breakthrough in 2D material transistors, signaling post-silicon semiconductor era

ASML, TSMC, and research institute imec have jointly demonstrated the first scaled complementary transistors built from 2D materials on standard manufacturing wafers, achieving a yield that makes commercial production look less like science fiction and more like an engineering timeline.

The results were presented in June 2026 at the IEEE/JSAP Symposium on VLSI Technology and Circuits.

What they actually built

The collaboration produced both n-type and p-type transistors at a contacted poly pitch of 50 nanometers. Contacted poly pitch (CPP) is essentially the repeating distance between transistor gates. Smaller CPP means you can pack more transistors into the same space, which is the whole point of Moore’s Law.

The n-type devices used molybdenum disulfide (MoS₂) as their channel material, while the p-type devices relied on tungsten disulfide (WS₂) or tungsten diselenide (WSe₂). These belong to a class of materials called transition metal dichalcogenides, which are atomically thin, two-dimensional crystals.

All of this was fabricated on industry-standard 300mm wafers using ASML’s single-patterning extreme ultraviolet (EUV) lithography.

The yield figure is arguably the most important number in the entire announcement: 94% of the transistors on the wafer were operational.

Both transistor types achieved an Imax/Imin ratio exceeding 10⁵ and exhibited very low off-currents at zero gate voltage. The WSe₂-based p-type transistors performed near record levels previously seen only in laboratory settings.

Why silicon needs a successor

Two-dimensional materials offer a potential escape route. Because they’re inherently just a few atoms thick, they can form ultra-thin channels without the performance penalties that plague silicon at similar dimensions. The practical challenge has always been manufacturing: growing these materials uniformly, patterning them precisely, and integrating them into existing fabrication processes without destroying their delicate properties.

The process is also back-end-compatible, meaning it could potentially be integrated into existing chip manufacturing flows rather than requiring entirely new fabs. The team noted that their approach is scalable and applicable to other 2D channel materials beyond the three demonstrated.

The lab-to-fab gap

TSMC’s Vice President and Chief Technology Officer, Dr. Min Cao, described the collaboration as pivotal in driving semiconductor innovation forward, with emphasis on de-risking and expediting the integration of novel materials into production environments.

Dr. Min Cao described the collaboration as pivotal in driving forward semiconductor innovation by de-risking and expediting new material integration into production.

ASML’s role is equally telling. The Dutch company holds a monopoly on EUV lithography systems, machines that cost upwards of $350 million each. By optimizing its single-patterning EUV process for 2D materials, ASML is positioning its tools for the post-silicon era.

Imec, the Belgium-based semiconductor research center, served as the third pillar of the collaboration, functioning as neutral ground where competing chipmakers and equipment suppliers collaborate on pre-competitive research.

What comes next

A 94% yield on a research demonstration is not the same as a 94% yield in high-volume manufacturing. Integration challenges remain: contact resistance between metal interconnects and 2D materials is notoriously difficult to optimize, and achieving uniformity across an entire 300mm wafer at production volumes will require further breakthroughs.

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