ASML and TSMC have announced a joint initiative to shift the semiconductor industry from 6-inch photomasks to a larger 12-inch format for High NA EUV lithography. The pilot line for these supersized masks is expected to come online by 2031, with full production readiness targeted for 2033.
The current 6-inch photomask format has been the industry standard for decades. The new 6-by-12-inch format is projected to deliver roughly a 40% increase in scanner productivity. A larger mask can print more chip area in a single exposure, and the 12-inch format eliminates stitching constraints entirely, opening the door to larger, more complex chip architectures that would be impractical or impossible with current mask sizes.
The High NA EUV timeline
TSMC plans to incorporate High NA EUV into its advanced-node high-volume manufacturing by 2030. The new 12-inch mask format is designed specifically for these next-generation systems. Samsung has set a goal to begin High NA EUV high-volume DRAM production by 2028. Intel has already started deploying High NA EUV tools in its production processes. Both Samsung and SK Hynix have expressed support for the ASML-TSMC mask initiative.
What this means for the chip supply chain
The shift to 12-inch masks ripples through the entire semiconductor supply chain, from mask blank manufacturers to pellicle suppliers to inspection equipment makers. Mask blanks will need to be manufactured at the new dimensions with the same extreme precision currently required for 6-inch formats. Inspection and metrology companies will similarly need to upgrade their tools, as scanning a 12-inch mask for defects takes more time and compute power than scanning a 6-inch one.
For ASML specifically, the initiative reinforces the company’s position as the sole supplier of EUV lithography systems. TSMC’s customers, which include Apple, Nvidia, AMD, and Qualcomm, will effectively commit as well, as their chip designs will be optimized for whatever process TSMC offers at the leading edge.
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