IBM Unveils Sub-1 Nanometer Chip With 100 Billion Transistors, Extending Moore’s Law

A New Architecture, Not Just a Smaller Chip

The announcement centers on what IBM calls the “nanostack,” an entirely new three-dimensional transistor architecture developed at its semiconductor research facility in Albany, New York. The design stacks and staggers transistors vertically in two bonded layers, using an ultra-thin dielectric material to separate them.

That approach differs fundamentally from the nanosheet technology IBM pioneered and the broader industry adopted. Nanosheets compressed features in two dimensions. Nanostack adds density in a third.

“We’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow.

What the Numbers Show

IBM’s published technical results, presented at VLSI 2026, report the following compared to IBM’s 2 nm chip from 2021:

• Nearly 2x transistor density
• Up to 50% more performance
• Up to 70% greater energy efficiency
• 40% improvement in SRAM scaling

The SRAM gain matters specifically for AI workloads. On-chip memory bandwidth is a limiting factor for AI accelerators, and better SRAM scaling lets chip designers fit more memory closer to the processor without adding area or power draw.

Why the 0.7 nm Label Needs Context

Modern process node numbers no longer correspond to literal physical dimensions. The transistor channel layers in IBM’s nanostack design measure roughly 5 nanometers thick, or about 15 silicon atoms. The 0.7 nm designation reflects the density and performance generation, not a direct measurement of every feature on the chip.

IBM acknowledged this directly. The company’s position is that the nanostack method delivers the effective gains expected from sub-1 nm scaling by going vertical rather than by shrinking every dimension closer to atomic limits.

A Path Forward for Moore’s Law

The semiconductor industry has faced mounting pressure as traditional two-dimensional shrinking hits physical constraints, including quantum tunneling, heat dissipation, and manufacturing cost. The pace of gains from pure lithography improvements has slowed.

IBM’s approach addresses this by adding density through 3D sequential integration. The company projects the nanostack architecture can support at least a decade of continued scaling from this point.

Dan Hutcheson of Techinsights said the development puts “another 10, 15 years on the roadmap.”

Major competitors like Intel, Samsung, and TSMC are pursuing related three-dimensional transistor strategies, including complementary FET designs. IBM’s announcement represents a working demonstration of a verified path at the sub-1 nm threshold.

The Albany Research Ecosystem

IBM conducts this work alongside partners including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions. The Albany facility will also house a High Numerical Aperture Extreme Ultraviolet lithography tool from ASML, a system required for the next phase of logic scaling.

IBM separately announced plans to form Anderon, a standalone quantum foundry intended to manufacture quantum wafers at commercial scale.

Timeline to Production

The nanostack chip remains a research prototype, though IBM confirmed it has demonstrated functional CMOS inverter operation with expected switching performance. IBM sees a path to production adoption in as early as five years, or roughly 2031.

The announcement does not signal an imminent product release. It signals that the industry’s next generation of hardware has a viable structural foundation.